1. Field of the Invention
The present invention relates to a floating-point arithmetic unit for performing arithmetic operations of floating-point data, and particularly to nearest value round-off according to IEEE Std 754 referred to as business standard.
2. Description of the Background Art
IEEE Std 754 is practically a business standard about the floating-point arithmetic operations, whose outstanding characteristics include the following four round-off modes:
(1) Nearest value round-off; PA1 (2) + Infinity round-off; PA1 (3) - Infinity round-off; and PA1 (4) Round-down.
When a floating-point arithmetic unit is configured with hardware to perform the above-mentioned round-off modes (1) to (4), the circuit configuration of the floating-point arithmetic unit will be complicated, leading to an increase in throughput.
FIG. 15 shows a part relating to round-off processing in such a floating-point arithmetic unit as is disclosed in Japanese Patent Laying-Open No.6-59858 as an example. The mantissa adder-subtracter portion MAP performs addition or subtraction of mantissa data A and B in two pieces of floating-point data. It is assumed here that the preceding and following processing system is configured so that the result of addition or subtraction is always presented as an absolute value, or a positive value. The ISB determination portion BJP determines whether the high-order three bits in the arithmetic result D made by the mantissa adder-subtracter portion MAP are "0" or not. The increment signal generating portion IP generates an increment signal for indicating a bit to be rounded up (an increment bit position) by using the determination result from the LSB determination portion BJP. The incrementer IMa applies increment to the bit indicated by the increment signal among the bits forming the arithmetic result D. The round-off decision portion RJPa decides whether to round by using the determination result from the LSB determination portion BJP. When the decision result from the round-off decision portion RJPa indicates round-off, the selector S1 selects and outputs the arithmetic result from the incrementer IMa. In other cases, it selects and outputs the arithmetic result D from the mantissa adder-subtracter portion MAP. The character MO indicates the output result from the selector S1.
However, in the arithmetic result made by the mantissa adder-subtracter portion MAP, the values are sequentially determined from the least significant bit side to the most significant bit side by carries occurring in this direction when adding the mantissa data A and B, for example. Accordingly, the increment signal generating portion IP has to wait until all bits in the arithmetic result D have been determined to specify the increment bit position. This waiting time increases the throughput.